A method of manufacturing a buried channel field effect transistor comprising the formation of a two-stage gate recess is known from the present-art Japanese Patent Application published under no. 61-89681/86 (also available in the form of an English abstract.
This known method comprises at least the following operations for realising the specific field effect transistor:
the formation of semiconductor layers (substrate) and of ohmic source and drain contacts, PA1 the formation of two superimposed masking layers: a first, purely dielectric layer or spacer layer, and a second, photoresist layer; PA1 etching of an opening having dimensions corresponding to the future gate in said masking layers, PA1 etching of a first, central recess in the subjacent semiconductor material down to a first depth, with transverse dimensions defined by those of the opening in the photoresist layer, PA1 lateral etching of the first spacer layer for delimiting in this layer an enlarged opening towards the sides, below the photoresist layer, PA1 etching of the subjacent semiconductor material, which etching comprises: PA1 wherein the subsequent etching steps carried out in the dielectric spacer layer and in the subjacent semiconductor material are carried out by means of selective chemical etching agents, one for the dielectric material, the other for the semiconductor material. PA1 realisation of a stack of layers on a substrate, with in that order: PA1 carrying out of etching steps for providing the first, central gate recess by self-alignment on the gate opening, comprising in that order: PA1 it is formed automatically during said etching step in a reproducible position, which is the upper surface of the active layer, and indeed over the entire surface of the substrate under treatment, PA1 it stops automatically said ongoing etching step at this level, which serves as a reproducible reference over the entire surface of the substrate under treatment, PA1 it is formed to a thickness which is sufficiently great for stopping the ongoing etching step, PA1 it is formed to a thickness which is sufficiently small for being readily eliminated without prolonging the process or disturbing surfaces already formed: typically, this stopper layer has a thickness of one or two atomic monolayers (0.3 to 0.6 nm). PA1 the implementation of subsequent etching steps, which include in that order:
renewed etching of the first, central recess down to a second depth, greater than the first, PA2 etching of a second, peripheral recess having transverse dimensions defined by those of the enlarged opening formed in the spacer layer, and having an intermediate depth between the surface of the semiconductor material and the bottom of the first, central recess, PA2 an active layer made of a semiconductor compound which a non-zero aluminium (Al) content in which a first, central recess is to be dug for receiving a Schottky gate contact, PA2 a cap layer made of a semiconductor material without aluminium (Al) for receiving the ohmic source and drain contacts of the transistor, PA2 a masking layer provided with an opening called gate opening, PA2 a first selective etching step with a first etching compound of fluorine (F) carried out in the cap layer through the gate opening and down to the upper surface of the active layer, on which a stopper layer of aluminium fluoride (AlF.sub.3) will be formed automatically through a reaction between the fluorine of the etching compound and the aluminium of the semiconductor compound of the active layer, PA2 elimination of the etching stopper layer of aluminium fluoride (AlF.sub.3), PA2 a second, non-selective etching step carried out in the active layer through the gate opening with a second etching agent until the first, central gate recess has been completed. PA2 a third selective etching step with the first etching compound of fluorine (F), carried out in the cap layer laterally only for forming the flanks of the second recess whose bottom is formed by the upper surface of the subjacent layer.
The result of these various operations is that the transistor exhibits a buried channel at two levels, with a first, central recess having the smaller dimension in transverse direction and a bottom level at greater depth for receiving the gate contact metal, and with a second, peripheral recess having the greater transverse dimension and a bottom level at an intermediate depth between that of the surface of the semiconductor material and that of the first, central recess.
It follows from the teachings in the cited document that two dielectric layers (the spacer and photoresist layers) are necessary for carrying out the known method satisfactorily; and that the final level of the first, central recess, which receives the gate contact, and which thus defines the effective depth of the transistor channel, is obtained by two successive chemical etching steps, i.e. a first etching step down to a first depth, and a second, repeated etching step down to a second depth.
Now the realisation of buried channel field effect transistors at two levels leads to manufacturing problems.
A first manufacturing problem lies in the fact that it is necessary in practice to realise several thousands of transistors which are absolutely identical simultaneously on one substrate of large diameter (at least 7 cm). If the means for controlling the etching depths to desired values are not provided, the etched depths will be on the one hand inaccurate and badly reproducible, and on the other hand these depths will be different at the centre and at the outside regions of the substrate. This results in the manufacture of transistors with dispersion in their electronic properties, and thus a lower useful manufacturing output.
The known method has the disadvantage that it leads to the realisation of the first, central recess in two successive etching steps, without indicating means for controlling the exact depth of each of these etching steps or means for automatically stopping the etching at an exact desired depth. The depth obtained by the two successive etching steps will thus be inaccurate and badly reproducible. The transistors realised on the total surface of a substrate will in addition exhibit dispersion in their characteristics. A second manufacturing problem lies in the fact that the designer of integrated circuits nowadays aims at transistors of a more complicated structure than the transistor realised by the known method. Nevertheless, these more complicated transistors must be manufactured in the smallest possible number of steps for reasons of economy.
The known method has the disadvantage that it utilizes two masking layers. Of these two layers, the photoresist layer is removed by lifting-off at the end of the process, after the manufacture of the metal gate contact, whereas the spacer layer is conserved as a protective layer. This conservation of the spacer layer, however, does not provide a sufficient protection because this layer has the disadvantage that it does not protect the gate region. The result is that this layer is useless in the final stage, when the manufacturer of the integrated circuit must provide a supplementary, effective protection layer which is not described. The formation of the spacer layer thus prolongs the known method in an unfavourable way.
Another manufacturing problem connected with the realisation of more complicated transistors than the one obtained by the known method lies in the fact that it is not indicated how the buried channel should be realised with a two-stage gate recess when different semiconductor materials disposed in successive layers are encountered during etching of this two-stage recess.
A solution to this latter problem must be found while also taking into account other problems as indicated above, i.e. a method must be provided wherein the etching depths are well controlled, well reproducible, substantially identical over the entire surface of the processed substrate, and the method must comprise as few steps as possible.